The hottest power-saving design extends the flexib

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Power saving design extends the flexibility of DDS to portable devices

the innovative design introduced in this paper combines the low-power characteristics and programmable analog-to-digital architecture to improve the modulation and output frequency control to a higher level

direct digital frequency synthesis (DDS) has the ability of fast frequency switching and modulation, and is widely used. However, when low power consumption and low cost are the main considerations, DDS often has to give way to analog phase locked loop (PLL). ADI's ad9913 changes this situation. It can not only provide fast switching and modulation flexibility of DDS Technology in the 125 MHz output bandwidth range, but also has low power consumption characteristics similar to PLL, with power consumption of only about 50 MW

dds solutions always have high power consumption. For example, AD9850, one of the first DDS products launched in the mid-1990s, is an integrated digital to analog converter (DAC), with a power consumption of 380 MW at 50 MHz output bandwidth. Ad9913 adopts innovative technology, which makes the appearance and accuracy of print molded parts very ideal, and its bandwidth power consumption is 20 times higher than that of AD9850

ad9913 brings three main benefits to portable and/or instrument applications: the low power consumption of 50 MW enables handheld and other portable applications to benefit from DDS technology; Programmable analog-to-digital architecture is an attractive feature for clock and instrument applications. It supports the synthesis of frequencies of any rational fraction (the ratio of two integers) at the same rate. Traditional DDS can only synthesize rational fraction frequencies whose denominator is a power of 2 at the same rate, such as 1/4 and 5/16, while ad9913 is not limited by the "power of 2". It can generate any rational fraction frequencies at the same rate, such as 1/10, 3/7 or 286/11487, as long as they are within the programming range of ad9913; Finally, like some early DDS products of ADI company, ad9913 can generate a variety of waveforms with great flexibility

ad9913 adopts a number of innovative power-saving technologies to achieve low power consumption. The first innovation involves the phase amplitude conversion part of DDS, which converts the instantaneous phase value generated by the phase accumulator into amplitude value according to a sine and/or cosine function. Traditionally, this task is performed by a read only memory (ROM) lookup table. However, with the increasing speed and complexity of DDS technology, the power consumption burden of ROM method has become unacceptable, which requires a proprietary angle rotation algorithm to rely on the computing engine to perform sine and/or cosine conversion. The angle rotation algorithm can be traced back to AD9850. Compared with ROM look-up table method, its power consumption is greatly reduced. If the angle rotation algorithm is not adopted, many early DDS products will need special heat dissipation packages to adapt to higher power consumption. In addition, heat dissipation considerations may also make us have to subtract many useful functions on existing DDS products, such as digital phase and/or frequency modulation of DDS output signals, using digital filtering to reduce sin (x)/x loss, and using multiple DDS cores for multi-channel applications

the second major power saving breakthrough can be attributed to ADI's patented phase interleaved DDS architecture (U.S. Patent No. 6587863). The energy saving and consumption reduction achieved by the phase rotation algorithm allows us to consider running multiple DDS cores on the same chip. We found that the power consumption of running multiple DDS cores at a low sampling rate is less than that of running a DDS core at a very high sampling rate. This is a very meaningful breakthrough, because DDS technology must be innovated to make full use of the new high-resolution (14 bit or higher) and high sampling rate (1 GHz or higher) digital to analog converter (DAC) cores. The interleaved DDS architecture enables design engineers to integrate multiple DDS cores that have reduced power consumption and run these cores at a sampling rate lower than that of the high-frequency DAC core. This innovative architecture, together with the adoption of 180 nm CMOS manufacturing process, has resulted in a significant increase in DDS output bandwidth, while power consumption is only slightly higher than that of the previous generation of low-frequency DDS products

however, for handheld and portable applications, even with the above innovations, the power consumption is still too large. In order to solve this problem, an innovation is needed. Therefore, we improve the angle rotation algorithm and introduce a new proprietary algorithm to further reduce the power consumption of DDS kernel. The new algorithm is combined with the design principle of focusing on low-power operation, which enables design engineers to achieve the desired low-power design goals. The new design principles include turning off all redundant internal clocks that are not required for a specific operating mode, and reducing the power consumption of each circuit module without reducing spectrum performance or improperly limiting bandwidth

the result of these innovative PP products with or without clear flame retardant performance requirements is ad9913, which has a sampling rate of up to 250 MHz and a power consumption of only 50 MW. At a sampling rate of 250 MHz, the available bandwidth is about 100 MHz. This output frequency capability and low power consumption characteristics of ad9913 make it particularly suitable for various radio control units, as well as wireless scanners for bar codes and radio frequency identification (RFID) tags. However, for applications requiring bandwidth above 100 MHz, an auxiliary PLL must be used for up conversion. Other handheld/portable applications that can benefit from low-power DDS technology include: Software Radio (SDR), remote or portable cable TV testing equipment, medical blood glucose meter, wireless fire alarm, as well as electronic measurement equipment such as spectrum analyzer and waveform generator

unique architecture

Figure 1 shows the low power consumption characteristics of ad9913 at the nominal output frequency of 100 MHz. The curve in the figure corresponds to three different working modes (single tone, linear scan and programmable modulus) and two REFCLK input driving modes (directly driven by differential source or directly driven by single ended source, and internal PLL is disabled)

ad9913 differs from traditional DDS devices in its unique programmable analog-to-digital architecture. Traditional DDS relies on the phase accumulator to distinguish the frequency, and the size (number of bits) of the accumulator determines the frequency resolution of DDS

if the phase accumulator has C-bit resolution, the frequency resolution provided by traditional DDS is fs/2c, where FS is the sampling rate of DDS. The digital tuning word M can be any integer from 0 to 2c-1 – 1. Theoretically, the allowable tuning word range is from 2c-1 to 2c-1, but this will lead to the synthesis of Nyquist mirror frequency (i.e. counter rotation phasor). Familiar DDS frequency synthesis equations can be listed according to the digital tuning word and DDS sampling rate (FS), where fo is the DDS output frequency:

fo/Fs = m/2c       (1)

because m must be an integer, traditional DDS can only synthesize 2c-1 unique frequencies for a given sampling rate. That is, when m = 0, the output frequency is 0 (DC); When m= 2c-1 – 1, the output frequency difference is only 0.5fs. All remaining output frequencies are increments of fs2c (frequency resolution of DDS). In most cases, such a precise frequency resolution is very satisfactory. For example, the ad9913 has a 32-bit accumulator with a frequency resolution of (250 MHz)/232, or about 0.058 Hz

now consider the case that a traditional DDS has a 32-bit accumulator, which is required to synthesize an output frequency that is exactly 1/1000 of the sampling rate. This means that fo/fs = 1/1000. Substitute it into the left side of equation 1 and solve m to get: M = 232/1000, or M = 296。 This m is obviously not an integer, but traditional DDS requires that M must be an integer value, so its closest integer value is used. This example is 4294967. The problem is that using this tuning word can not accurately synthesize the frequency of 0.001fs, but about 0 Frequency of FS. In some applications, such as network clock applications, this slight deviation is unacceptable

the C-bit phase accumulator in traditional DDS causes the modulus (n) to be fixed, that is, n =2c. The programmable module DDS architecture has ingeniously improved the phase accumulator, and the shipment of downstream finished products has been improved, so that the module can be any integer that meets the condition of 1 ≤ n ≤ 2C. In other words, the value of N can be set by the user. For programmable analog-to-digital DDS architecture, when n = 1 or n = 2, the synthetic frequency is 0 Hz, so the minimum available analog-to-digital (used to generate output other than DC) is n = 3

like traditional DDS, programmable modular DDS also requires m in equation 1 to be an integer. However, since n is programmable, the DDS output frequency equation becomes:

fo/fs = m/n       (2)

equation 2 looks flat at first glance, and it automatically rises from its integrated horizontal position; When the speed drops below 70km/h, it is not surprising, but actually quite meaningful. Consider selecting a specific modulus n = 2C. At this time, the frequency set that can be synthesized is the same as that of traditional DDS. However, programmable analog-to-digital DDS includes not only the whole frequency set of traditional DDS, but also many other frequencies. This is because each specific n value (from 3 to 2C) corresponds to m (1 ≤ M

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